Digital phase lock loops (DPLLs) are commonly used to create oscillatory signals in phase with but at a frequency multiple of a reference oscillation. Analog to digital (A/D) converters use DPLLs to generate high frequency oscillations used in over-sampling in a sigma-delta conversion process. Data converters that sample serial digital data and convert the data to an analog format also require a high frequency sampling oscillation to synchronize its sampling to the rate of the incoming digital data.
One particular application using a DPLL is a digital phone system. In the digital phone system, radio frequency transmissions containing digital data are transmitted between a base unit and a portable unit. The digital data coupled to the analog signal typically comprises digital data organized in a serial format as a data frame. Data frames are transmitted on a periodical basis from the base unit to the portable unit such that the portable unit may create a reference oscillation based upon the data frames and will be able to receive data consistently. Based upon the data frames, a DPLL in the portable unit creates a sampling signal based upon the reference oscillation but at a much higher frequency. A communication processor within the portable unit uses the sampling signal to convert data between the digital format and an analog format. Typically, the digital data contains voice data, and the communication processor converts the data between an analog format that is conveyed to and received from a user and the digital format that is received from and conveyed to the base unit.
DPLLs typically comprise a phase detector, a loop filter, a digital oscillator, and a feedback divider. In operation, the digital oscillator constructs a first oscillation from a fixed frequency clock. Typically, the fixed frequency clock is somewhere in the 10 megahertz range and the first oscillation is in the one megahertz range although these frequencies change from installation to installation. The first oscillation inputs to the divider which creates both a feedback oscillation and a sampling signal that is use by the communication processor in the sampling process. The phase detector and loop filter operate to force the feedback oscillation into phase with the reference oscillation. In this fashion, the first oscillation and sampling signal are also in phase with the reference oscillation.
Traditionally, specifications for the DPLL required that the fixed frequency clock be a certain frequency and have a certain tolerance in order to create the correct feedback signal and sampling signal. Thus, the selection of a particular fixed frequency clock has been important. Clocks having differing frequencies are commonly used today and could otherwise be available to serve as the fixed frequency clock. Unfortunately, because DPLLs have heretofore been designed to operate with a specific fixed frequency clock to produce the feedback oscillation, the limitation has been a drawback.
Thus, there exists a need in the art for an apparatus and method for allowing a DPLL to function properly with a variety of fixed frequency clock frequencies such that a single DPLL design could be used in a variety of installations.